Conventionally, as is disclosed in, for example, Japanese Patent Application Laid-Open No. 2008-269487, there has been disclosed an art that is for reducing the power consumption during engine stop for an engine controlling electronic control device including a microcomputer adopting at least one of a multicore configuration and a cache memory-mounted configuration. A CPU and a cache memory are both elements with large power consumption in a microcomputer. Thus, in the above described conventional art, during engine operation, the mode in which the CPU core and the cache memory are fully used to exhibit the maximum processing capability is selected, whereas during engine stop, the mode for decreasing the busy count of the CPU core and the use amount of the cache memory more than at the time of engine operation is selected.